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(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
FEATURES
* Designed for Very Low-Power applications * Offered in Tiny GREEN/RoHS compliant packages o 6-pin DFN (2.0mmx1.3mmx0.6mm) o 6-pin SC70 (2.3mmx2.25mmx1.0mm) o 6-pin SOT23 (3.0mmx3.0mmx1.35mm) * Input Frequency: o Reference Input: 1MHz to 200MHz o Non PLL mode, Ref input down to 10kHz * Accepts >0.1V reference signal input voltage * Output frequency up to 55MHz CMOS. o <65MHz @ 1.8V operation o <90MHz @ 2.5V operation o <125MHz @ 3.3V operation * One programmable I/O pin can be configured as Power Down (PDB) input, output Enable (OE), or Frequency Selection Switching input. * Disabled outputs programmable as HiZ or Active Low. * Low current consumption: o <1.0mA with 27MHz & 32kHz outputs o < 5 A when PDB is activated * Single 1.8V, 2.5V, or 3.3V 10% power supply * Operating temperature range from -40C to 85C
DESCRIPTION
The PL611s-19 is a low-cost general purpose frequency synthesizer and a member of PhaseLink's Factory Programmable `Quick Turn Clock (QTC)' family. PhaseLink's PL611s-19 offers the versatility of using a single Reference Clock input and producing up to two (kHz or MHz) system clock outputs. Designed for low-power applications with very stringent space requirement, PL611s-19 consumes <1.0mA, while producing 2 distinct outputs of 27MHz and 32kHz. The power down feature of PL611s-19, when activated, allows the IC to consume less than 5 A of power. PL611s-19 fits in a small DFN, SC70, or SOT23 package. Cascading of the PL611s-19 with other PhaseLink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. In addition, one programmable I/O pin can be configured as Power Down (PDB) input, Output Enable (OE), or Frequency switching (FSEL). CLK1 can be programmed as (CLK0, FREF, FREF /2) output.
BLOCK DIAGRAM
FIN FREF R-Counter (5-bit) M-Counter (8-bit) Phase Detector Charge Pump Loop Filter
F VCO = F REF * (2 * M/R)
VCO
P-Counter (14-bit) FOUT = F VCO / (2 * P)
Programmable Function
CLK [0:1]
Programming Logic
OE, PDB, FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
KEY PROGRAMMING PARAMETERS
CLK Output Frequency FOUT = FREF * M / (R * P) Where M = 8 bit R = 5 bit P = 14 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: * Low: 4mA * Std: 8mA (default) * High: 16mA Programmable Input/Output One output pin can be configured as: * * * * OE - input FSEL - input PDB - input
HiZ or Active Low disabled state
PIN CONFIGURATION AND DESCRIPTION
CLK1 FIN CLK1 GND 1 2 3 6 5 4 CLK1 OE, PDB, FSEL VDD OE, PDB, FSEL CLK0 FIN DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm)
1 2 3
6 5 4
CLK0 VDD OE, PDB, FSEL
PL611s-19 PL611s-19 PL611s-19 PL611s-19
1 2 3
6 5 4
CLK0 GND GND FIN VDD
PL611s-19 PL611s-19 PL611s-19 PL611s-19
SC70 70SC70-6L (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx
PL611s-19 PL611s-19 PL611s-19 PL611s-19
SOT23 23SOT23-6L (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm
Name
CLK1 GND FIN
Pin Assignment DFN SC70 SOT Pin# Pin# Pin #
2 3 1 1 5 3 1 2 3
Type
I/O P I Programmable Clock Output GND connection Reference input pin
Description
OE, PDB, FSEL
6
2
4
O
This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down input (PDB) or On-the-Fly Frequency Switching Selector (FSEL). This pin has an internal 60K pull up resistor for OE, PDB & FSEL. The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode.
VDD CLK0
5 4
4 6
5 6
P O
VDD connection Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE 1 0 N/A N/A PDB N/A N/A 1 0 Osc. On On On Off PLL On Off On Off CLK0 On HiZ or Active Low On HiZ or Active Low CLK1 On On On HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
FUNCTIONAL DESCRIPTION
PL611s-19 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-19 accepts a reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-19 to deliver any PLL generated frequency, FREF (Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-19 are mentioned below: PLL Programming The PLL in the PL611s-19 is fully programmable. The PLL is equipped with an 5-bit input frequency divider (R-Counter), and an 8-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 14-bit post VCO divider (P-Counter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. Clock Output (CLK0) The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), FREF (Ref Clk Frequency) output, or FREF/(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. Clock Output (CLK1) The output of CLK1 can be configured as: FREF - Reference ( Ref Clk ) Frequency FREF / 2 CLK0 CLK0 / 2 When using the OE function CLK1 will remain "Always On" and will not be disabled when OE is pulled low. When using the PDB function CLK1 will be disabled along with CLK0. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz.
Programmable I/O (OE/PDB/FSEL)
The PL611s-19 provides one programmable I/O pin which can be configured as one of the following functions: Output Enable (OE) The Output Enable feature allows the user to enable and disable CLK0 clock output by toggling the OE pin. CLK1 remains active when OE is pulled low. The OE pin incorporates a 60k pull up resistor giving a default condition of logic "1". The OE feature can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode. Power-Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL611s-19 into "Sleep Mode". When activated (logic `0'), PDB `Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <5 A of power. The PDB pin incorporates a 60k pull up resistor giving a default condition of logic "1". The PDB feature can be programmed to allow the output to float (Hi Z), or to operate in the `Active low' mode. Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-19 to switch between two pre-programmed outputs allowing the device "On the Fly" frequency switching. The FSEL pin incorporates a 60k pull up resistor giving a default condition of logic "1".
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 3
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention @ 85C Storage Temperature Ambient Operating Temperature*
SYMBOL
VDD VI VO
MIN.
MAX.
7 VDD+0.5 VDD+0.5 260 150 85
UNITS
V V V C Year C C
-0.5 -0.5 -0.5
10
TS
-65 -40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ VDD =3.3V Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Output Frequency Settling Time Output Enable Time @ VDD =2.5V @ VDD =1.8V Internally AC/DC coupled (High Frequency) Internally AC/DC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz @ VDD =3.3V @ VDD =2.5V @ VDD =1.8V At power-up (after VDD increases over 1.62V) OE Function; Ta=25 C, 15pF Load 1 0.9 0.1
CONDITIONS
MIN.
TYP.
MAX.
200 166 133 VDD VDD 125 90 65 2 10
UNITS
MHz Vpp Vpp MHz MHz MHz ms ns ms ns ns % ps
PDB Function; Ta=25 C, 15pF Load Output Rise Time 15pF Load, 10/90% VDD, High Drive, 3.3V Output Fall Time 15pF Load, 90/10% VDD, High Drive, 3.3V Duty Cycle PLL Enabled, @ VDD /2 Period Jitter,Pk-to-Pk* With capacitive decoupling between VDD and (measured from 10K samples) GND. * Note: Jitter performance depends on the programming parameters.
45
1.2 1.2 50 70
2 1.7 1.7 55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 4
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs PLL Off: Supply Current, Dynamic, with Loaded CMOS Output PLL Off: Supply Current, Dynamic, with Loaded CMOS Output PLL Off: Supply Current, Dynamic with Loaded CMOS Output PLL Off: Supply Current, Dynamic with Loaded CMOS Output Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive Output Current, Standard Drive Output Current, High Drive
SYMBOL
IDD IDD IDD IDD IDD IDD IDD IDD VDD VOL VOH IOSD IOSD IOHD
CONDITIONS
@ VDD =3.3V, load=15pF @ VDD =2.5V, load=10pF @ VDD =1.8V, load=5pF @ VDD =3.3V, load=15pF @ VDD =2.5V, load=15pF @ VDD =1.8V, load=15pF @ VDD =1.8V, load=15pF When PDB=0 27MHz, 27MHz, 27MHz, 32kHz, 32KMHz, 32kHz, Hz output,
MIN.
TYP.
4.0 2.7 0.9 0.6 0.5 0.2 0.2
MAX.
UNITS
mA mA mA mA mA mA mA
5 1.62 3.63 0.4
A V V V mA mA mA
IOL = +4mA Standard Drive IOH = -4mA Standard Drive VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V
VDD - 0.4 4 8 16
* Note: Please contact PhaseLink, if super-low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 5
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL611s-19 as short as possible, as well as keeping all other traces as far away from it as possible. - When a reference input clock is generated from a crystal, place the PL611s-19 `FIN' as close as possible to the `Xout' crystal pin. This will reduce the cross-talk between the reference input and the other signals. - Place a 0.01 F~0.1 F decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or `stripline', to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually `striplines' are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the `stripline' trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or for additional layout assistance. DFN-6L Evaluation Board
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 6
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6 L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L
D1
Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC
Pin1 Dot
E
H
D
A2 A A1 e b C L
Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC
Pin1 Dot
E
H
D
A2 A A1 e b C L
Symbol A A1 A3 b e D E D1 E1 L
Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
b
e Pin 6 ID Chamfer E1 E
D
L Pin1 Dot A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 7
(Preliminary)PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock TM
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range
PL611s-19-XXX X X X
PART NUMBER
3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT-6L Part /Order Number PL611s-19-XXXGC-R PL611s-19-XXXUC-R PL611s-19-XXXTC-R
R=TAPE and REEL
TEMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking XXX XXX 19XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel)
Note: `XXX' designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 8

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